1. Field of the Invention
The invention relates to a data transfer apparatus including a serializer converting parallel data into serial data based on clock signal.
2. Description of the Related Art
Serial transfer interfaces such as SATA (Serial Advanced Technology Attachment) and PCIe (PCI Express) have a plurality of lanes for transmission and reception of data. In terms of the power consumption and noises, the number of signal lines distributing clock signals to each lane is preferably small. In addition, it is required to align the phases of clocks among the lanes (align the timing of reset) in order to perform data transfer correctly.
In order to solve the above problems, Japanese Laid Open Patent Application No. 1999-127141, for example, suggests a communication system including a parent module for generating a clock used in a module and a reset pulse with a regular interval and a child module for generating a clock used in the child module and resetting with the predetermined interval based on the reset pulse, wherein the clock in the parent module and the clock in the child module are synchronized with each other.
In the above communication system described in the Japanese Patent Application Laid-Open No. 1999-127141, each of the parent module and the child module has a clock generation circuit (PLL circuit), and there is a problem in that the system has a large circuitry size and consumes much power.